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ADE7754
INTERRUPTS
ADE7754 interrupts are managed through the interrupt status
register (STATUS[15:0], Address 10h) and the interrupt enable
register (IRQEN[15:0], Address 0Fh). When an interrupt event
occurs in the ADE7754, the corresponding flag in the interrupt
status register is set to Logic 1. See the Interrupt Status Register
section. If the enable bit for this interrupt in the interrupt enable
register is Logic 1, then the IRQ logic output goes active low.
The flag bits in the interrupt status register are set irrespective
of the state of the enable bits. In order to determine the source
of the interrupt, the system master (MCU) should perform a
read from the reset interrupt status register with reset. This is
achieved by carrying out a read from Address 11h. The IRQ
output goes logic high on completion of the interrupt status
register read command. See the Interrupt Timing section. When
carrying out a read with reset, the ADE7754 is designed to
ensure that no interrupt events are missed. If an interrupt event
occurs just as the interrupt status register is being read, the
event will not be lost and the IRQ logic output is guaranteed to
go high for the duration of the interrupt status register data
transfer before going logic low again to indicate the pending
interrupt.
Using Interrupts with an MCU
The timing diagram in Figure 47 illustrates a suggested imple-
mentation of ADE7754 interrupt management using an MCU.
At time t 1 , the IRQ line goes active low indicating that one or
more interrupt events have occurred. The IRQ logic output
should be tied to a negative edge triggered external interrupt on
the MCU. On detection of the negative edge, the MCU should
be configured to start executing its interrupt service routine
(ISR). On entering the ISR, all interrupts should be disabled
using the global interrupt enable bit. At this point the MCU
external interrupt flag can be cleared in order to capture inter-
rupt events that occur during the current ISR. When the MCU
interrupt flag is cleared, a read from the reset interrupt status
register with reset is carried out. This causes the IRQ line to be
reset logic high (t 2 ). See the Interrupt Timing section. The reset
interrupt status register contents are used to determine the
source of the interrupt(s) and therefore the appropriate action to
be taken. If a subsequent interrupt event occurs during the ISR
(t 3 ), that event will be recorded by the MCU external interrupt
flag being set again. On returning from the ISR, the global
interrupt enable bit will be cleared (same instruction cycle) and
the external interrupt flag will cause the MCU to jump to its
ISR once again. This will ensure that the MCU does not miss
any external interrupts.
Interrupt Timing
The Serial Interface section should be reviewed first before
reviewing interrupt timing. As previously described, when the
IRQ output goes low, the MCU ISR must read the interrupt
status register in order to determine the source of the interrupt.
When reading the interrupt status register contents, the IRQ
output is set high on the last falling edge of SCLK of the first
byte transfer (read interrupt status register command). The IRQ
output is held high until the last bit of the next 8-bit transfer is
shifted out (interrupt status register contents). See Figure 48. If
an interrupt is pending at this time, the IRQ output will go low
again. If no interrupt is pending, the IRQ output will remain high.
MCU
INT. FLAG SET
IRQ
t 1
t 2
t 3
PROGRAM
SEQUENCE
JUMP TO
ISR
GLOBAL
INTERRUPT
MASK
CLEAR MCU
INTERRUPT
FLAG
READ
STATUS WITH
RESET (11h)
ISR ACTION
(BASED ON STATUS CONTENTS)
ISR RETURN
GLOBAL INTERRUPT
MASK RESET
JUMP TO
ISR
Figure 47. Interrupt Management
CS
t 1
t 9
SCLK
DIN
0
0
0
1
0
0
0
1
t 11
t 12
DOUT
DB15
DB8
DB7
DB0
IRQ
READ STATUS REGISTER COMMAND
Figure 48. Interrupt Timing
–30 –
STATUS REGISTER CONTENTS
REV. 0
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